Frank Verhoorn
About Frank Verhoorn
Frank Verhoorn serves as the Verification Lead for DRAM Controller Products at Rambus, where he has worked since 2016. He has extensive experience in engineering and verification roles, primarily at Intel Corporation, and holds advanced degrees in Electrical Engineering from Stanford University and MIT.
Current Role at Rambus
Frank Verhoorn serves as the Verification Lead for DRAM Controller Products at Rambus. He has held this position since 2016, contributing to the verification strategy and goals for the DRAM Controller product group. His role includes managing a team of two full-time verification engineers and occasionally overseeing additional contract engineers. Verhoorn has architected and led the implementation of a scalable, object-oriented UVM testbench for DRAM Controller products, which has enhanced the verification environment.
Previous Experience at Intel Corporation
Frank Verhoorn has extensive experience at Intel Corporation, where he worked in various capacities for 25 years from 1991 to 2016. His roles included Supercomputer Chipset Components - Fullchip Technical Lead, Engineering Manager for the LAN Access Division, Server Chipset Development Manager, and Architectural Verification Manager. Throughout his tenure, he contributed to significant projects and managed teams focused on chipset development and verification.
Education and Expertise
Frank Verhoorn holds a Master of Science in Electrical Engineering (MSEE) from Stanford University, where he studied digital and analog MOS circuit design, digital logic design, and layout. He also earned a Bachelor of Science in Electrical Engineering (BSEE) from the Massachusetts Institute of Technology, focusing on uProcessor-based digital design, semiconductor devices, and analog and digital feedback/control. Additionally, he has obtained an Agile Scrum Certification from Lizzy Morris.
Work History at Northwest Logic and Other Companies
Before his current role at Rambus, Frank Verhoorn worked as Verification Lead for DRAM products at Northwest Logic for six months in 2016. He also held a position at Infochip Systems, Inc. from 1988 to 1991 and interned at HP as a PA-RISC CPU Design Engineer from 1986 to 1988. His diverse experience across these companies has contributed to his expertise in verification and engineering management.