Manjunath Goud L
About Manjunath Goud L
Manjunath Goud L is a Senior Member of Technical Staff at Rambus, with extensive experience in ASIC verification and chip fabric protocols. He has worked at various companies, including Cerium Systems and HCL Technologies, and holds a Bachelor of Engineering in Electronics and Communication Engineering.
Work at Rambus
Manjunath Goud L currently holds the position of Senior Member of Technical Staff at Rambus. He has been with the company since 2021 and is based in Bengaluru, Karnataka, India. In this role, he focuses on various technical aspects of chip verification and validation, contributing to the development of advanced semiconductor technologies.
Previous Experience at Cerium Systems
Prior to his current role, Manjunath worked at Cerium Systems as a Senior Verification Engineer from 2020 to 2021. He also served as an Application Specific Integrated Circuit Verification Engineer at the same company from 2018 to 2019. His responsibilities included verifying complex integrated circuits and ensuring compliance with design specifications.
Experience at HCL Technologies
Manjunath worked at HCL Technologies as an ASIC Verification Engineer from 2016 to 2018. During his tenure, he was involved in the verification of application-specific integrated circuits, focusing on ensuring the functionality and performance of various chip designs.
Education and Expertise
Manjunath Goud L completed his Bachelor of Engineering (B.E.) in Electronics and Communication Engineering at the University of Vivesvaraya College of Engineering from 2012 to 2016. He also attended TGM High School in Adoni, where he achieved his Secondary School Certificate (SSC) from 2003 to 2010. His technical expertise includes knowledge of chip fabric protocols such as AMBA-AXI, AHB, APB, and JTAG, as well as a strong understanding of cache coherence protocols and instruction set architectures.
Technical Skills and Competencies
Manjunath possesses extensive skills in verifying CXL.Cache, CXL.Memory, and CXL.IO Protocol's transaction layer using UVM Verification Methodology. He has hands-on experience in verifying PCIe Gen4 and Gen5 physical layers and demonstrates strong abilities in debugging and analyzing RTL simulations. Additionally, he has experience in developing test bench components.