Mike Volz
About Mike Volz
Mike Volz is a Verification Lead with extensive experience in integrated circuit design verification, currently working at Rambus since 2019. He has previously held positions at companies such as Intel Corporation, IBM, and Synopsys, and possesses a strong background in Object-Oriented methodologies and automated testing techniques.
Work at Rambus
Mike Volz has been serving as the Verification Lead at Rambus since 2019. In this role, he is responsible for overseeing verification processes and ensuring the quality of integrated circuit designs. His work involves utilizing advanced methodologies and tools to enhance verification efficiency. He is based in Hillsboro, Oregon, where he continues to contribute to the company's projects.
Previous Experience at Intel Corporation
Prior to his current position, Mike Volz worked at Intel Corporation as a Verification Engineer from 2016 to 2018. During his two-year tenure in Hillsboro, Oregon, he focused on verification tasks that supported the development of Intel's products. His experience at Intel contributed to his expertise in verification methodologies.
Education and Expertise
Mike Volz holds a Bachelor of Science degree from Oregon State University, which he completed from 2016 to 2019. He also earned a Master of Engineering degree from Portland State University. His educational background supports his expertise in verification methodologies, including Object-Oriented methodologies, Verilog, and SystemVerilog.
Career Background
Mike Volz has a diverse career in verification and engineering roles. He began as a Systems Engineer at IBM from 2000 to 2002. He then worked at Focus Enhancements as a Design Verification Engineer from 2004 to 2008, followed by a position at Synopsys as a Senior R&D Engineer from 2008 to 2013. He continued his career at Rohde & Schwarz as a Senior Verification Engineer from 2013 to 2016 before joining Intel and later Rambus.
Verification Skills and Methodologies
Mike Volz possesses a range of skills in verification, including expertise in integrated circuit design verification, behavioral verification, and constrained random stimulus generation. He utilizes automated self-checking mechanisms and coverage-driven testing methodologies. His proficiency in VMM, UVM, OpenVera, and SV Assertions enhances his ability to deliver high-quality verification results.