Mike Werstlein
About Mike Werstlein
Mike Werstlein is a Senior Design Engineer with extensive experience in x86 hardware virtualization and embedded system design. He has worked for notable companies including Intel, Microsoft, and Rambus, and holds a Bachelor of Science in Electrical and Electronics Engineering from Oregon State University.
Work at Rambus
Mike Werstlein has been employed at Rambus as a Senior Design Engineer since 2023. His role involves leveraging his extensive experience in hardware design and engineering to contribute to the development of advanced technologies. Located in Hillsboro, Oregon, he is part of a team focused on creating innovative solutions in the semiconductor industry.
Previous Experience at Intel
Prior to joining Rambus, Mike Werstlein worked at Intel for 21 years as a Staff ASIC/FPGA Design Engineer from 1999 to 2020. During his tenure in the Portland, Oregon area, he specialized in x86 hardware virtualization, particularly VT-d, and contributed to various projects related to x86 server products.
Education and Expertise
Mike Werstlein earned a Bachelor of Science in Electrical and Electronics Engineering from Oregon State University, studying from 1986 to 1991. His educational background, combined with his professional experience, has equipped him with expertise in designing x86 server products and embedded system design using Atmel AVR and 8051 microcontrollers.
Career Background
Mike Werstlein has a diverse career in engineering, having held positions at several notable companies. He worked as a Senior Design Engineer at Level One Communications from 1993 to 1999, and as a Design Engineer at National Semiconductor from 1991 to 1993. He also served as an RTL Design Engineer at Microsoft from 2020 to 2023, further expanding his skills in networking products and packet processing.
Technical Skills and Proficiencies
Mike Werstlein possesses a strong technical skill set, including proficiency in Verilog RTL, C, Python, and shell scripting languages. He has extensive experience in designing networking products, focusing on Ethernet 802.3 physical and MAC layers, as well as TCP/IP layers 2-4 packet processing. His ability to thrive in team environments emphasizes his commitment to project success.